You remember Legos, right? We are young enough to have played with them as a kid.
Intel recently announced its next microprocessor architecture, code named “Sandy Bridge,” and it’s decidedly Lego-like—it’s a collection of elements designed to be snapped together in different combinations to create different chips for different markets. Sort of like using your bucket of Legos to build either a modest home or a towering skyscraper.
All this snapping is done on one 32-nanometer piece of silicon (which is nice, it is using smaller tech to start). In addition to the processing cores, Sandy Bridge has cutely named cache boxes—one per core—integrated graphics, a memory controller, and housekeeping and input/output controllers. The sweetness is that the way these elements communicate makes it easy as pie—well, as easy as silicon pie—to add or subtract cores, swap out one graphics unit for another, and so forth. Doing so will allow Intel to build both low-cost, low-power chips for entry-level laptops and many-cored mondo processors for data centers like Apple’s new $1 billion North Carolina megacenter that’ll feed your Apple TV.
How many cores are we talking about? Well, Intel hasn’t ofﬁcially said, but during its recent Developers Forum, one of its engineering bigwigs referred to 2-, 4-, 10-, and 16-core models. Those 16-core beasties will certainly be able to wipe the ﬂoor with the standard 4-core model that Intel showcased at its developer soirée—but cranking away inside banks of server racks, 16-core chips won’t need graphics capable of playing Starcraft II: Wings of Liberty. So for its server chips, Intel will be able to swap out the consumer graphics unit with a lower-performing one. It’ll also likely strip out such niceties as the consumer chip’s nifty video transcoder, which includes what Intel calls “consumer electronics–quality” image enhancers.
But back to the way the elements talk to one another—it’s the system mentioned above that makes all this swapping possible. Called a “ring bus,” it ﬁrst appeared on an Intel Xeon server chip—not the one in the Mac Pro, but one for servers with four CPUs per motherboard—and Intel improved it and made it the on-chip communication system for Sandy Bridge. One central tenet of the ring bus’s operational scheme makes adding and subtracting cores and cache boxes easy. Simply put, the ring bus cares not a g how many elements it connects. Data zips around it like cars on a freeway. When one chip element—core, cache, graphics, or housekeeping—wants to send a message or piece of data to another element, it simply waits for a break in the trafﬁc and hops into the lane. In chip talk, this is called local arbitration—as opposed to central arbitration, where some bit of additional chippery needs to know where everything is at all times. As you might imagine, scaling a centrally arbitrated scheme from 2 to 16 cores and cache boxes would be a colossal pain. After Sandy Bridge systems begin appearing early next year, expect to eventually see a healthy variety in the line—which, by the way, will be ofﬁcially called the 2nd Generation Intel Core Processors.
One ﬁnal note: although Intel promises that Sandy Bridge’s graphics will be a vast improvement over its current tepid integrated graphics, don’t expect them to bankrupt AMD/ATI or Nvidia. As an Intel graphics honcho said at the forum, “I don’t see high-end discrete graphics cards going away, nor do I see Formula One race cars going away just because we built Priuses.”
Just as a disclaimer, this was mostly… almost entirely lifted from the Mac Life December 2010 edition. This is not original writing.